Education
- Bachelor (110/110 cum Laude, December 2010) and Master Degree(110/110 cum Laude, December 2012) in Ingegneria Elettronica (Electronic Engineering) at the University of Bologna.
- PhD in Ingegneria Elettronica (Electronic Engineering) with the Department of Electrical and Information Engineering "Guglielmo Marconi" (DEI), advisor Prof. Luca Benini (June 2016)
Academic career
From September 2022, he is Tenure-Track Assistant Professor (RTD-B) at the Department of Electrical and Information Engineering "Guglielmo Marconi" (DEI), University of Bologna, where previously he was Junior Assistant Professor (RTD-A) from June 2020. Previously, from July 2016 to June 2020, he was Research Assistant at the Energy-Efficient Embedded Systems Laboratory (University of Bologna) and Postdoctoral Researcher at the Integrated Systems Laboratory (ETH Zurich).
Teaching activity
He is the holder of courses related to digital architectures at the Master's degree in Electrical Engineering, taught in Italian and English (EBIT): Digital Architectures for Signal Processing (mod. 1, from A.Y. 2022/23), Architectures for Artificial Intelligence (mod. 2, from A.Y. 2020/21). He was also the holder of mod. 2 of Statistics and Architectures for Big Data Processing (from A.Y. 2020/21 to 2023/24) and mod. 2 of the course on Electronic Systems Architecture and Programming at the Master's degree in Electrical Engineering and Telecommunications from A.Y. 2021/22 to 2022/23.
From the academic year 2017/2018 to 2019/2020, he was an academic tutor for the course of Elettronica T-A taught by Prof. Andrea Bartolini at the degree in Industrial Engineering. He also performs from 2015/16 activities as a student assistant (including frontal lessons) for the course on Hardware-Software Design of Embedded Systems taught by Prof. Luca Benini.
Scientific activity
His scientific activity focuses on the development of digital architectures for hardware acceleration on heterogeneous System-on-Chip, combining dedicated logic with programmable and configurable architectures, particularly for Artificial Intelligence applications on devices with extremely low power consumption or high efficiency. As architect and RTL and front-end designer, he has participated in the development of more than 15 research prototype System-on-Chip, particularly in collaboration with the Integrated Systems Laboratory at ETH Zurich (list: http://asic.ethz.ch/authors/Francesco_Conti.html ), resulting in various publications in top-tier venues (including ISSCC 2021 and 2023, ESSCIRC 2023, and three articles on IEEE Journal of Solid-State Circuits).
He has participated as first author or co-author to more than 90 publications on scientific journals or international conferences in the field of digital circuits (IEEE Journal of Solid-State Circuits, ISSCC, IEEE TCAS-I, IEEE TCAS-II, DAC, DATE, IEEE TCAD), also performing activities as a reviewer. Since 2022 he is Associate Editor of IEEE Transactions on Computer-Aided Design of Circuits and Systems. He is member of the TPC of DATE since edition 2022, co-chair of topic E3 for DATE 2024 and chair of topic E3 for DATE 2025. In 2017, 2018, and 2019 he was co-chair of the Low-Power Embedded Systems workshop (LP-EMS). He was visiting PhD student at the Robust Systems Group led by Prof. Subhasish Mitra at Stanford University (USA).
List of publications: https://dblp.org/pid/50/8932-1.html
Awards
- IEEE TCAS-I Darlington Best Paper Award (2020)
- Hipeac Technology Transfer Award (2018)
- Best Paper Award at ESWEEK (2018)
- Best Paper Award at ASAP (2014)
- Best Paper Award at Embedded Systems Workshop (2014)
