E. Flamand; D. Rossi; F. Conti; I. Loi; A. Pullini; F. Rotenberg; L. Benini, GAP-8: A RISC-V SoC for AI at the Edge of the IoT, in: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018, pp. 1 - 4 (atti di: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Milan, Italy, 10-12 July 2018) [Contributo in Atti di convegno]
Andri, Renzo; Cavigelli, Lukas; Rossi, Davide; Benini, Luca, Hyperdrive: A systolically scalable binary-weight CNN Inference Engine for mW IoT End-Nodes, in: Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, IEEE Computer Society, 2018, 2018-, pp. 509 - 515 (atti di: 17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, hkg, 2018) [Contributo in Atti di convegno]
Mauro A.D.; Rossi D.; Pullini A.; Flatresse P.; Benini L., Independent body-biasing of P-N transistors in an 28nm UTBB FD-SOI ULP near-threshold multi-core cluster, in: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Institute of Electrical and Electronics Engineers Inc., 2018, pp. 1 - 3 (atti di: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Hyatt Regency, San Francisco Airport, usa, 2018) [Contributo in Atti di convegno]
Di Mauro, Alfio; Rossi, Davide; Pullini, Antonio; Flatresse, Philippe; Benini, Luca, Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology, in: Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 2018, 2018-, pp. 1 - 1 (atti di: 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, ita, 2018) [Contributo in Atti di convegno]
Zolfaghari H.; Rossi D.; Nurmi J., Low-latency packet parsing in software defined networks, in: 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 2018, pp. 1 - 6 (atti di: 4th IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018, est, 2018) [Contributo in Atti di convegno]
Pullini, Antonio; Rossi, Davide; Loi, Igor; Di Mauro, Alfio; Benini, Luca, Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing, in: ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., 2018, pp. 130 - 133 (atti di: 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, Dresden, 2018) [Contributo in Atti di convegno]
Meloni, Paolo; Capotondi, Alessandro; Deriu, Gianfranco; Brian, Michele; Conti, Francesco; Rossi, Davide; Raffo, Luigi; Benini, Luca, NEURAghe: Exploiting CPU-FPGA synergies for efficient and flexible CNN inference acceleration on zynQ SoCs, «ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS», 2018, 11, Article number: 18, pp. 1 - 24 [articolo]Open Access
Azarkhish, Erfan*; Rossi, Davide; Loi, Igor; Benini, Luca, Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes, «IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS», 2018, 29, Article number: 8038819, pp. 420 - 434 [articolo]Open Access
Nouri, Sajjad*; Rossi, Davide; Nurmi, Jari, Power mitigation of a heterogeneous multicore architecture on FPGA/ASIC by DFS/DVFS techniques, «MICROPROCESSORS AND MICROSYSTEMS», 2018, 63, pp. 259 - 268 [articolo]
Fabio Montagna, Abbas Rahimi, Simone Benatti, Davide Rossi, Luca Benini, PULP-HD: Accelerating brain-inspired high-dimensional computing on a parallel ultra-low power platform, in: PROCEEDINGS OF THE 2018 55TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), NEW YORK, IEEE, 2018, pp. 1 - 6 (atti di: 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA - USA, JUN 24-28, 2018) [Contributo in Atti di convegno]Open Access
Schiavone P.D.; Rossi D.; Pullini A.; Di Mauro A.; Conti F.; Benini L., Quentin: an ultra-low-power PULPissimo SoC in 22nm FDX, in: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Institute of Electrical and Electronics Engineers Inc., 2018, pp. 1 - 3 (atti di: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Hyatt Regency, San Francisco Airport, usa, 2018) [Contributo in Atti di convegno]
Martino, Dazzi; Pierpaolo, Palestri; Davide, Rossi; Andrea, Bandizioly; Igor, Loi; David, Bellasi; Luca, Benini, Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes, in: Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes, 2018, pp. 1 - 4 (atti di: IEEE ISCAS 2018, Firenze, May 27, 2018 – May 30, 2018) [Contributo in Atti di convegno]
Tagliavini, Giuseppe; Rossi, Davide; Marongiu, Andrea; Benini, Luca, Synergistic HW/SW Approximation Techniques for Ultralow-Power Parallel Computing, «IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS», 2018, 37, pp. 982 - 995 [articolo]Open Access
Loi, Igor; Capotondi, Alessandro; Rossi, Davide; Marongiu, Andrea; Benini, Luca, The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores, «IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS», 2018, 4, pp. 99 - 112 [articolo]Open Access
Andri, Renzo; Cavigelli, Lukas; Rossi, Davide; Benini, Luca, YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration, «IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS», 2018, 37, pp. 48 - 60 [articolo]Open Access
