Denkinger B.W.; Ponzina F.; Basu S.S.; Bonetti A.; Balasi S.; Ruggiero M.; Peon-Quiros M.; Rossi D.; Burg A.; Atienza D., Impact of memory voltage scaling on accuracy and resilience of deep learning based edge devices, «IEEE DESIGN & TEST», 2020, 37, Article number: 8868100, pp. 84 - 92 [articolo]Open Access
De Giovanni, Elisabetta; Montagna, Fabio; Denkinger, Benoit W.; Machetti, Simone; Peon-Quiros, Miguel; Benatti, Simone; Rossi, Davide; Benini, Luca; Atienza, David, Modular Design and Optimization of Biomedical Applications for UltraLow Power Heterogeneous Platforms, «IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS», 2020, 39, pp. 3821 - 3832 [articolo]Open Access
Schiavone P.D.; Rossi D.; Liu Y.; Benatti S.; Luan S.; Williams I.; Benini L.; Constandinou T., Neuro-PULP: A Paradigm Shift Towards Fully Programmable Platforms for Neural Interfaces, in: Proceedings - 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020, Institute of Electrical and Electronics Engineers Inc., 2020, pp. 50 - 54 (atti di: 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020, ita, 2020) [Contributo in Atti di convegno]
Di Mauro A.; Rossi D.; Pullini A.; Flatresse P.; Benini L., Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI, «INTEGRATION», 2020, 72, pp. 194 - 207 [articolo]Open Access
Garofalo A.; Rusci M.; Conti F.; Rossi D.; Benini L., PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors, «PHILOSOPHICAL TRANSACTIONS OF THE ROYAL SOCIETY OF LONDON SERIES A: MATHEMATICAL PHYSICAL AND ENGINEERING SCIENCES», 2020, 378, Article number: 20190155, pp. 1 - 22 [articolo]Open Access
Prasad, Rohit; Das, Satyajit; Martin, Kevin J. M.; Tagliavini, Giuseppe; Coussy, Philippe; Benini, Luca; Rossi, Davide, TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE, in: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Institute of Electrical and Electronics Engineers Inc. (IEEE), «PROCEEDINGS DESIGN, AUTOMATION, AND TEST IN EUROPE CONFERENCE AND EXHIBITION», 2020, pp. 1067 - 1072 (atti di: 23rd Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, Grenoble, France, 9-13 March 2020) [Contributo in Atti di convegno]Open Access
Garofalo, Angelo; Tagliavini, Giuseppe; Conti, Francesco; Rossi, Davide; Benini, Luca, XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions, in: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Institute of Electrical and Electronics Engineers Inc. (IEEE), 2020, pp. 186 - 191 (atti di: Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, Grenoble, France, 9-13 March 2020) [Contributo in Atti di convegno]Open Access
Andrea Bartolini,
Davide Rossi,
Antonio Mastrandrea,
Christian Conficoni,
Simone Benatti,
Andrea Tilli,
Luca Benini, A PULP-based Parallel Power Controller for Future Exascale Systems, in: 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Piscataway, NJ, IEEE, 2019, pp. 771 - 774 (atti di: 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2019), Genova, Italy, 27-29 November 2019) [Contributo in Atti di convegno]Open Access
Das, Satyajit; Martin, Kevin J. M.; Rossi, Davide; Coussy, Philippe; Benini, Luca, An Energy-Efficient Integrated Programmable Array Accelerator and Compilation flow for Near-Sensor Ultralow Power Processing, «IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS», 2019, 38, pp. 1095 - 1108 [articolo]Open Access
Zolfaghari H.; Rossi D.; Nurmi J., An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks, in: 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 2019, pp. 1 - 7 (atti di: 5th IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019, fin, 2019) [Contributo in Atti di convegno]
Kartsch, V.; Tagliavini, G.; Guermandi, M.; Benatti, S.; Rossi, D.; Benini, L., BioWolf: A Sub-10-mW 8-Channel Advanced Brain-Computer Interface Platform with a Nine-Core Processor and BLE Connectivity, «IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS», 2019, 13, Article number: 8758394, pp. 893 - 906 [articolo]
Tagliavini G.; MacH S.; Rossi D.; Marongiu A.; Benini L., Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA, in: Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition (DATE), Institute of Electrical and Electronics Engineers Inc. (IEEE), 2019, pp. 654 - 657 (atti di: 22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019, Firenze, Italy, 25 – 29 March 2019) [Contributo in Atti di convegno]Open Access
Glaser F.; Haugou G.; Rossi D.; Huang Q.; Benini L., Hardware-Accelerated Energy-Efficient Synchronization and Communication for Ultra-Low-Power Tightly Coupled Clusters, in: Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019, Institute of Electrical and Electronics Engineers Inc., 2019, pp. 552 - 557 (atti di: 22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019, Firenze Fiera, ita, 2019) [Contributo in Atti di convegno]
Andri R.; Cavigelli L.; Rossi D.; Benini L., Hyperdrive: A Multi-Chip Systolically Scalable Binary-Weight CNN Inference Engine, «IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS», 2019, 9, Article number: 8668446, pp. 309 - 322 [articolo]Open Access
Pullini A.; Rossi D.; Loi I.; Tagliavini G.; Benini L., Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing, «IEEE JOURNAL OF SOLID-STATE CIRCUITS», 2019, 54, Article number: 8715500, pp. 1970 - 1981 [articolo]Open Access
