Daniele Bortolotti;Davide Rossi;Andrea Bartolini;Luca Benini, A variation tolerant architecture for ultra low power multi-processor cluster, in: 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013 IEEE, 2013, pp. 32 - 38 (atti di: 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013, Karlsruhe; Germany, 9-11 September 2013) [Contributo in Atti di convegno]
D. Rossi; C. Mucci; F. Campi; S. Spolzino; L. Vanzolini; H. Sahlbach; S. Whitty; R. Ernst; W. Putzke-Röming; R. Guerrieri, Application Space Exploration of a Heterogeneous
Run-Time Configurable Digital Signal Processor, «IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS», 2013, 21, Article number: 6156496, pp. 193 - 205 [articolo]
Andrea Manuzzato; Fabio Campi; Davide Rossi; Valentino Liberali; Davide Pandini, Exploiting body biasing for leakage reduction: A case study, in: 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013, pp. 133 - 138 (atti di: 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Natal, 5-7 Aug. 2013) [Contributo in Atti di convegno]
A. Grasset; P. Millet; P. Bonnot; S. Yehia; W. Putzke-Roeming; F. Campi; A. Rosti; M. Huebner; N. S. Voros; D. Rossi, The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform, «INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING», 2011, 39, pp. 328 - 356 [articolo]
C.Brunelli; F.Garzia; D.Rossi; J.Nurmi, A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations, «JOURNAL OF SYSTEMS ARCHITECTURE», 2010, 56, pp. 38 - 47 [articolo]
D. Rossi; F. Campi; S. Spolzino; S. Pucillo; R. Guerrieri, A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing, «IEEE JOURNAL OF SOLID-STATE CIRCUITS», 2010, 45, n.8, pp. 1615 - 1626 [articolo]
D.Rossi; F.Campi; A.Deledda; S.Spolzino; S.Pucillo, A Heterogeneous Digital Signal Processor Implementation for Dynamically Reconfigurable Computing, in: Proceedings of IEEE Custom Integrated Circuit Conference, s.l, IEEE, 2009, pp. 641 - 644 (atti di: IEEE Custom Integrated Circuit Conference, San Jose, California, U.S.A., 13-16 Sept. 2009) [Contributo in Atti di convegno]
D. Rossi; F. Campi; A. Deledda; C. Mucci; S. Pucillo; S. Whitty; R. Ernst; S. Chevobbe; S. Guyetant; M. Kühnle; M. Hübner; J. Becker; W. Putzke-Roeming, A Multi-Core Signal Processor for Heterogeneous Reconfigurable Computing, in: Proceedings of 2009 International Symposium on System-on-Chip, s.l, IEEE, 2009, pp. 106 - 109 (atti di: International Symposium on System-on-Chip, Tampere, Finland, 5-7 Oct. 2009) [Contributo in Atti di convegno]
F. Campi; R. Konig; M. Dreschmann; M. Neukirchner; D. Picard; M. Juttner; E. Schuler; A. Deledda; D. Rossi; A. Pasini; M. Hubner; J. Becker; R. Guerrieri, RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip, in: Proceedings, Piscataway, NJ, IEEE, 2009, pp. 110 - 113 (atti di: International Symposium on System-on-Chip, 2009. SOC 2009., Tampere, Finland, 5 -7 October 2009) [Contributo in Atti di convegno]
C. Mucci; D. Rossi; F. Campi; L. Ciccarelli; M. Pizzotti; L. Perugini; L. Vanzolini; T. De Marco; M. Innocenti, The Dream Digital Signal Processor: Architecture, programming model and application mapping, in: N. VOROS A. ROSTI M. HUEBNER, Dynamic System Reconfiguration in Heterogeneous Platforms, MILAN, Springer, 2009, pp. 49 - 61 [capitolo di libro]
F. Campi; A. Deledda; D. Rossi; M. Coppola; L. Pieralisi; R. Locatelli; G. Maruccia; T. De Marco; F. Ries; M. Kühnle; M. Hübner; J. Becker, The MORPHEUS Data Communication and Storage Infrastructure, in: N. VOROS A. ROSTI M. HUEBNER, Dynamic System Reconfiguration in Heterogeneous Platforms, MILAN, Springer, 2009, pp. 93 - 105 [capitolo di libro]
C. Brunelli; F. Campi; C. Mucci; D. Rossi; T. Ahonen; J. Kylliäinen; F. Garzia; J. Nurmi, Design space exploration of an open-source, IP-reusable, scalable floating-point engine for embedded applications, «JOURNAL OF SYSTEMS ARCHITECTURE», 2008, 54, pp. 1143 - 1154 [articolo]
F. Garzia; C. Brunelli; D. Rossi; J. Nurmi, Implementation of a floating-point matrix-vector multiplication on a reconfigurable architecture, in: Proceedings of IEEE International Symposium on Parallel & Distributed Processing, 2008. IPDPS 2008., s.l, IEEE, 2008, pp. 1 - 6 (atti di: IEEE International Symposium on Parallel & Distributed Processing, 2008. IPDPS 2008., Miami, Florida, U.S.A., 14-18 April 2008) [Contributo in Atti di convegno]
C. Brunelli; F. Cinelli; D. Rossi; J. Nurmi, A VHDL model and Implementation of a Coarse-Grain Reconfigurable Coprocessor for a RISC Core, in: Ph. D. Research in Microelectronics and Electronics, OTRANTO, s.n, 2006, pp. 229 - 232 (atti di: Ph. D. Research in Microelectronics and Electronics, Otranto, 11 Sep. 2006) [Contributo in Atti di convegno]
C. Brunelli; F. Garzia; J. Nurmi C. Mucci; F. Campi; D. Rossi, A FPGA Implementation of An Open-Source Floating-Point Computation System, in: Proceedings of 2005 International Symposium onSystem-on-Chip., TAMPERE, s.n, 2005, pp. 29 - 32 (atti di: International Symposium onSystem-on-Chip, Tampere, Finland, 17 Nov. 2005) [Contributo in Atti di convegno]
