J. M. Cazeaux; D. Rossi; M. Omaña; A. Chatterjee; C. Metra, On-Transistor Level Gate Sizing for Increased Robustness to Transient Faults, in: Proceedings 11th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, K. Roy, L. Anghel, M. Nicolaidis, 2005, pp. 23 - 28 (atti di: 11th IEEE International On-Line Testing Symposium, Saint Raphael, Francia, 6-8 luglio 2005) [Contribution to conference proceedings]
R. Aitken; H. Ito; C.Metra; N. Park, Proceeding of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., LOS ALAMITOS, IEEE, 2005, pp. v - 602 . [Editorship]
C. Metra; K. Roy; L. Anghel; M. Nicolaidis, Proceedings 11th IEEE International On-Line Testing Symposium, LOS ALAMITOS, IEEE, 2005, pp. v - 326 . [Editorship]
J. M. Cazeaux; D. Rossi; C. Metra, Self-Checking Voter for High Speed TMR Systems, «JOURNAL OF ELECTRONIC TESTING», 2005, 21, pp. 377 - 389 [Scientific article]
M. Omaña; D. Rossi; J. M. Cazeaux; TM. Mak; C. Metra, The Other Side of the Timing Equation: a Result of Clock Faults, in: Proceeding of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., LOS ALAMITOS, R. Aitken, H. Ito, C. Metra, N. Park, 2005(atti di: 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., Monterey, CA, USA, 3-5 Ottobre 2005) [Contribution to conference proceedings]
M. Nicolaidis; C. Metra; L. Anghel; K. Roy, Welcome, in: C. METRA K. ROY L. ANGHEL AND M. NICOLAIDIS, Proceedings 11th IEEE International On-Line Testing Symposium., LOS ALAMITOS, C. metra, K. Roy, L. Anghel and M. Nicolaidis, 2005, pp. x - x [Brief introduction]
M. Nicolaidis; J.P. Teixeira; R. Leveugle; C. Metra, 10th IEEE International On-Line Testing Symposium, 2004. [Exhibition]
Patent n. EP04100850.9, AC/DC FAULT TOLERANT CODE.
C. Metra; T. M. Mak; M. Omaña, Are Our Design For Testability Features Fault Secure ?, in: Proceedings Design, Automation and Test in Europe Conference and Exhibition, LOS ALAMITOS, G. Gielen, J. Figueras, 2004, 1, pp. 714 - 715 (atti di: Design, Automation and Test in Europe Conference and Exhibition (DATE'04), Parigi, Francia, 16-20 Febbraio 2004) [Contribution to conference proceedings]
A. Ivanov; F. lombardi; C. Metra, Design & Test of Computers, LOS ALAMITOS, IEEE, 2004, pp. 269 - 342 (Special Issue on Special Issue on Testing at MultiGbps Rates). [Research monograph]
M. Omaña; D. Rossi; C. Metra, Fast and Low-Cost Clock Deskew Buffer, in: 2004 Proceedings of 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, LOS ALAMITOS, R.Aitken, and A.Salsano, and R.Velazco, and X.Sun, 2004, pp. 202 - 210 (atti di: 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Cannes, Francia, 10-13 ottobre 2004) [Contribution to conference proceedings]
C. Metra; T. M. Mak; M. Omaña, Fault secureness need for next generation high performance microprocessor design for testability structures, in: Proceedings of the 1st conference on Computing frontiers, NEW YORK, ACM press, 2004, pp. 444 - 450 (atti di: Conference On Computing Frontiers, Ischia, Italy, April 14-16) [Contribution to conference proceedings]
C. Metra; M. Sonza Reorda, Guest Editorial, in: C. METRA M. SONZA REORDA, Journal of Electronic Testing, On-line Testing, S.L., C. Metra, M. Sonza Reorda, 2004, pp. 463 - 463 [Brief introduction]
A. Ivanov; F. Lombardi; C. Metra, Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates, «IEEE DESIGN & TEST OF COMPUTERS», 2004, 21, pp. 274 - 276 [Scientific article]
C Metra; A. Ferrari; M. Omaña; A. Pagni, Hardware Reconfiguration Scheme for High Availability Systems, in: Proceedings 10th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, R. Leveugle, M. Nicolaidis, J. Teixeira, 2004, pp. 161 - 166 (atti di: 10th IEEE International On-Line Testing Symposium, Madeira, Portugal, 12-14 luglio 2004) [Contribution to conference proceedings]
