C. Metra; M. Omaña; TM Mak; S. Tam, Novel Approach to Clock Fault Testing for High Performance Microprocessors, in: Proceedings of 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, LOS ALAMITOS, P. Prinetto, H. Wunderlich, 2007, pp. 441 - 446 (atti di: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Berkeley, California, 6-10 May, 2007) [Contribution to conference proceedings]
C. Metra; M. Omaña; TM Mak; S. Tam, Novel Compensation Scheme for Local Clocks of High Performance Microprocessors, in: International Test Conference 2007 Proceedings, LOS ALAMITOS, J. E. Sibert, D. Young, 2007, pp. 1 - 9 (atti di: International Test Conference 2007, Santa Clara, California, 23-25 October, 2007) [Contribution to conference proceedings]
M. Favalli; C. Metra, Pulse Propagation for the Detection of Small Delay Defects, in: Proceedings Design, Automation and Test in Europe Conference and Exhibition, LOS ALAMITOS, R. Lauwereins, D. Sciuto, 2007(atti di: Design, Automation and Test in Europe Conference and Exhibition (DATE 2007), Nice, France, 16-20 April, 2007) [Contribution to conference proceedings]
X. Ma; J. Huang; C. Metra; F. Lombardi, Reversible and Testable Circuits for Molecular QCA Design, in: MOHAMMAD TEHRANIPOOR, Frontiers in Electronic Testing, NORWELL, MA, Springer US, 2007, pp. 157 - 202 [Chapter or essay]
X. Ma; J. Huang; C. Metra; F. Lombardi, Testing Reversible One-Dimensional QCA Arrays for Multiple Faults, in: Proceedings of 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, LOS ALAMITOS, C. Bolchini, Y-B Kim, A. Salsano, N. Touba, 2007, pp. 469 - 477 (atti di: 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Rome, Italy, 26-28 September, 2007) [Contribution to conference proceedings]
C. Metra; D. Rossi; TM Mak, Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?, «IEEE TRANSACTIONS ON COMPUTERS», 2007, 56, pp. 415 - 428 [Scientific article]
C. Metra; M. Nicolaidis; R. Leveugle; R. Aitken, 12th IEEE International On-Line Testing Symposium, 2006. [Exhibition]
J.M. Cazeaux; D. Rossi; C. Metra; F. Lombardi, A Novel Dual-Walled CNT Bus Architecture with Reduced Cross-Coupling Features, in: Proceedings IEEE Conference on Nanotechnology, LOS ALAMITOS, C. Lau, D. Janes, S. Bandyopadhyay, M. Cahay, 2006, 1(atti di: IEEE Conference on Nanotechnology (IEEE-NANO 2006), Cincinnati, Ohio, USA, 16-20 July, 2006) [Contribution to conference proceedings]
D. Rossi; C. Steiner; C. Metra, Analysis of the Impact of Bus Implemented EDCs on On-Chip SSN, in: Proceedings Design, Automation and Test in Europe Conference and Exhibition, LOS ALAMITOS, D. Sciuto, G. Gielen, 2006, 1, pp. 59 - 64 (atti di: Design, Automation and Test in Europe Conference and Exhibition (DATE 2006), Messe Munich, Germany, 6-10 March, 2006) [Contribution to conference proceedings]
C. Metra; D. Rossi; M. Omaña; J.M. Cazeaux; TM Mak, Can Clock Faults Be Detected Through Functional Test ?, in: Proceeding of the 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, LOS ALAMITOS, B. Straube, O. Novak, 2006, 1, pp. 168 - 173 (atti di: 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'06), Prague, Czech Republic, April 18-21, 2006) [Contribution to conference proceedings]
D. Rossi; M. Omaña; C. Metra; A. Pagni, Checker No-Harm Alarm Robustness, in: Proceedings 12th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, M. Nicolaidis, R. Aitken, R. Leveugle, 2006, 1, pp. 275 - 280 (atti di: 12th IEEE International On-Line Testing Symposium, Como, Italy, 10-12 July, 2006) [Contribution to conference proceedings]
M. Omaña; J.M. Cazeaux; D. Rossi; C. Metra, Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects, in: Proceedings Design, Automation and Test in Europe Conference and Exhibition, LOS ALAMITOS, D. Sciuto, G. Gielen, 2006, 1, pp. 170 - 175 (atti di: Design, Automation and Test in Europe Conference and Exhibition (DATE 2006), Messe Munich, Germany, 6-10 March, 2006) [Contribution to conference proceedings]
C. Metra; M. Omaña; D. Rossi; J.M. Cazeaux; TM Mak, Path (Min) delay Faults and Their Impact on Self-Checking Circuits' Operation, in: Proceedings 12th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, M. Nicolaidis, R. Aitken, R. Leveugle, 2006, 1, pp. 17 - 22 (atti di: 12th IEEE International On-Line Testing Symposium, Como, Italy, 10-12 July, 2006) [Contribution to conference proceedings]
R. Leveugle; R. Aitken; C. Metra; M. Nicolaidis, Proceedings 12th IEEE International On-Line Testing Symposium, LOS ALAMITOS, IEEE, 2006, pp. v - 294 . [Editorship]
X. Ma; J. Huang; C. Metra; F. Lombardi, Testing Reversible 1D Arrays of Molecular QCA, in: Proceedings of 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, LOS ALAMITOS, N. Park, H. Ito, A. Salsano, N. Touba, 2006, 1, pp. 71 - 79 (atti di: 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Washington DC, USA, 4-6 October, 2006) [Contribution to conference proceedings]
