I. Loi; F. Angiolini; L. Benini, Supporting vertical links for 3D networks on chip: toward an automated design and analysis flow, in: Proceedings of the Nano-Net Conference 2007,, s.l, s.n, 2007, pp. 1 - 5 (atti di: Nano-Net Conference 2007, Catania, Italy, Sep 24-26, 2007) [Contributo in Atti di convegno]
S. Murali; P. Meloni; D. Atienza; S. Carta; L. Benini; G. De Micheli; L. Raffo, Synthesis of Predictable Networks-on-Chip Based Interconnect Architectures for Chip Multi-Processors, «IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS», 2007, 15, n° 8, pp. 869 - 880 [articolo]
Atienza D. ; Bobba S.K. ; Poli M. ; De Micheli G. ; Benini L., System-Level Design for Nano-Electronics, in: Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on, s.l, IEEE Press, 2007, pp. 747 - 751 (atti di: 14th IEEE International Conference on Electronics, Circuits and Systems, 2007. ICECS 2007., Marrakech, 11-14 Dec. 2007) [Contributo in Atti di convegno]
A. Sathanur; A. Pullini; L. Benini; A.Macii; E. Macii; M. Poncino, Timing-driven row-based power gating, in: Proceedings of the 2007 international symposium on Low power electronics and design, NEW YORK, NY, ACM Press, 2007, pp. 104 - 109 (atti di: International symposium on Low power electronics and design.
Session: Power considerations at the physical level, Portland, OR, USA, 2007) [Contributo in Atti di convegno]
R. Tamhankar; S. Murali; S. Stergiou; A. Pullini; F. Angiolini; L. Benini; G. De Micheli, Timing-Error-Tolerant Network-on-Chip Design Methodology, «IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS», 2007, 26, num. 7, pp. 1297 - 1310 [articolo]
P.G. Del Valle; D. Atienza; I. Magan; J.G. Flores; E.A. Perez; J.M. Mendias; L. Benini; G. De Micheli, A Complete Multi-Processor System-on-Chip FPGA-Based Emulation
Framework, in: Proceedings of 14th Annual IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), s.l, s.n, 2006, pp. 140 - 145 (atti di: 14th Annual IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Nice, France, October 2006) [Contributo in Atti di convegno]
G. Pari; M. Ruggiero; A. Guerri; L. Benini; M. Milano;D. Bertozzi; A. Andrei, A Cooperative, accurate solving framework for optimal allocation, scheduling and frequency selection on energy-efficient MPSoCs, in: Proc. of the International Symposium on System-on-Chip 2006, TAMPERE, Jari Nurmi, 2006, -, pp. 183 - 186 (atti di: International Symposium on System-on-Chip 2006, Tampere Finland, Nov. 2006) [Contributo in Atti di convegno]
D. Atienza; P. G. Del Valle; G. Paci; F. Poletti; L. Benini; G. De Micheli; J. M. Mendias, A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip, in: Proceedings of the 43rd annual conference on Design automation.
Session 36: electrical and thermal issues in FPGAS, NEW YORK, NY, ACM Press, 2006, pp. 618 - 623 (atti di: Annual ACM IEEE Design Automation Conference, San Francisco, CA, USA, 2006) [Contributo in Atti di convegno]
S. Murali; D. Atienza; L. Benini; G. De Micheli, A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip, in: Proceedings of the 43rd annual conference on Design automation table of contents. Session 49: analysis and optimization issues in NoC design, NEW YORK, NY, ACM Press, 2006, pp. 845 - 848 (atti di: Annual ACM IEEE Design Automation Conference, San Francisco, CA, USA, 2006) [Contributo in Atti di convegno]
I. Al Khatib; F. Poletti; D. Bertozzi; L. Benini; M. Bechara; H. Khalifeh; A. Jantsch; R. Nabiev, A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration, in: 2006 Design Automation Conference, PISCATAWAY, NJ, IEEE, 2006, pp. 125 - 130 (atti di: 2006 Design Automation Conference, San Francisco, CA, USA, 24-28 July 2006) [Contributo in Atti di convegno]
S. Yoon; L. Benini; G. De Micheli, A Pattern Mining Method for High-throughput Lab-on-a-chip Data Analysis, in: Design Automation Methods and Tools for Microfluidics-Based Biochips, BERLIN, Springer, 2006, pp. 280 - 300 [capitolo di libro]
S. Yoon; L. Benini; G. De Micheli, A pattern Mining Method for High-throughput Lab-on-chip Data Analysis, «IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS», 2006, 25 , Issue: 2, pp. 358 - 377 [articolo]
P. Zappi; E. Farella; L. Benini, A PIR based wireless sensor node prototype for surveillance applications, in: Adjunct Proceedings Of European Workshop on Wireless Sensor Networks (EWSN 06), s.l, s.n, 2006, pp. 26 - 27 (atti di: European Workshop on Wireless Sensor Networks (EWSN 06), Zurich – CH, 13-15 Feb. 2006) [Contributo in Atti di convegno]
E. Farella; A. Pieracci; L. Benini; A. Acquaviva, A Wireless Body Area Sensor Network for Posture Detection, in: Computers and Communications, 2006. ISCC '06. Proceedings. 11th IEEE Symposium on, LOS ALAMITOS, CALIFORNIA, IEEE Computer Society Press, 2006(atti di: Computers and Communications, 2006. ISCC '06. 11th IEEE Symposium on, **, 2006) [Contributo in Atti di convegno]
L. Benini; D. Bertozzi; A. Guerri; M.Milano, Allocation, Scheduling and Voltage Scaling for Energy Aware MPSOCs, in: Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems, Heidelberg, Springer, «LECTURE NOTES IN COMPUTER SCIENCE», 2006, 3990, pp. 44 - 58 (atti di: Integration of AI and OR techniques in Constraint Programming for Combinatorial Optimization problems, Cork, Ireland, June 2006) [Contributo in Atti di convegno]
