Chen J.; Loi I.; Flamand E.; Tagliavini G.; Benini L.; Rossi D., Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters, «IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS», 2023, 31, Article number: 10048762 , pp. 456 - 469 [Scientific article]Open Access
Mirsalari, Seyed Ahmad; Tagliavini, Giuseppe; Rossi, Davide; Benini, Luca, TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes, in: 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023, pp. 1 - 2 (atti di: Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 17-19 April 2023) [Abstract]
Montagna F.; Mach S.; Benatti S.; Garofalo A.; Ottavi G.; Benini L.; Rossi D.; Tagliavini G., A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics, «IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS», 2022, 33, pp. 1038 - 1053 [Scientific article]Open Access
Tabanelli E.; Tagliavini G.; Benini L., Optimizing Random Forest Based Inference on RISC-V MCUs at the Extreme Edge, «IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS», 2022, 41, pp. 4516 - 4526 [Scientific article]Open Access
Nadalini D.; Rusci M.; Tagliavini G.; Ravaglia L.; Benini L.; Conti F., PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning, in: Embedded Computer Systems: Architectures, Modeling, and Simulation, Springer, 2022, 13511, pp. 200 - 216 (atti di: 22nd International Conference, SAMOS 2022, Samos, Greece, July 3–7, 2022) [Contribution to conference proceedings]Open Access
Bruschi N.; Tagliavini G.; Conti F.; Abadal S.; Cabellos-Aparicio A.; Alarcon E.; Karunaratne G.; Boybat I.; Benini L.; Rossi D., Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference, in: 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022, pp. 170 - 173 (atti di: Artificial Intelligence Circuits and Systems (AICAS), Incheon, Korea, Republic of Korea, 13-15 June 2022) [Contribution to conference proceedings]Open Access
Rossi D.; Conti F.; Eggiman M.; Mauro A.D.; Tagliavini G.; Mach S.; Guermandi M.; Pullini A.; Loi I.; Chen J.; Flamand E.; Benini L., Vega: A Ten-Core SoC for IoT Endnodes with DNN Acceleration and Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode, «IEEE JOURNAL OF SOLID-STATE CIRCUITS», 2022, 57, pp. 127 - 139 [Scientific article]Open Access
Garofalo A.; Ottavi G.; Di Mauro A.; Conti F.; Tagliavini G.; Benini L.; Rossi D., A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode, in: ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings, New York, Institute of Electrical and Electronics Engineers Inc., 2021, pp. 267 - 270 (atti di: 47th IEEE European Solid State Circuits Conference, ESSCIRC 2021, Grenoble/ France, 6 September - 9 September 2021) [Contribution to conference proceedings]Open Access
Burrello, Alessio; Garofalo, Angelo; Bruschi, Nazareno; Tagliavini, Giuseppe; Rossi, Davide; Conti, Francesco, DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs, «IEEE TRANSACTIONS ON COMPUTERS», 2021, 70, pp. 1253 - 1268 [Scientific article]Open Access
Mazzoni B.; Benatti S.; Benini L.; Tagliavini G., Efficient Transform Algorithms for Parallel Ultra-Low-Power IoT End Nodes, «IEEE EMBEDDED SYSTEMS LETTERS», 2021, 13, pp. 210 - 213 [Scientific article]Open Access
Florian Glaser; Giuseppe Tagliavini; Davide Rossi; Germain Haugoug; Qiuting Huang; Luca Benini, Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters, «IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS», 2021, 32, pp. 633 - 648 [Scientific article]Open Access
Bruschi, Nazareno; Haugou, Germain; Tagliavini, Giuseppe; Conti, Francesco; Benini, Luca; Rossi, Davide, GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors, in: 2021 IEEE 39th International Conference on Computer Design (ICCD), New York, IEEE, 2021, pp. 409 - 416 (atti di: IEEE International Conference on Computer Design (ICCD), Storrs, CT, USA, 24-27 Oct. 2021) [Contribution to conference proceedings]Open Access
Matteo Perotti; Giuseppe Tagliavini; Stefan Mach; Luca Bertaccini; Luca Benini, RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors, in: ETH Bibliography, SAMOS XXI - International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2021, pp. . - . (atti di: SAMOS XXI - International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, Samos Island, Greece, 5-7 july 2021) [Contribution to conference proceedings]
Parisi E.; Barchi F.; Bartolini A.; Tagliavini G.; Acquaviva A., Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers, in: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Los Alamitos, Institute of Electrical and Electronics Engineers Inc., 2021, pp. 878 - 883 (atti di: 2021 Design, Automation and Test in Europe Conference and Exhibition, DATE 2021, Grenoble, FR, 2021) [Contribution to conference proceedings]Open Access
Montagna, Fabio; Tagliavini, Giuseppe; Rossi, Davide; Garofalo, Angelo; Benini, Luca, Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-core MCUs, in: Architecture of Computing Systems, Cham, Springer, 2021, 12800, pp. 167 - 182 (atti di: 34th International Conference on Architecture of Computing Systems, Online, 7-8 Giugno 2021) [Contribution to conference proceedings]Open Access
